WHY IT MATTERS

Verilog is the most popular language used to build systems in a top-down HDL-based design flow. SystemVerilog offers several valuable features for such design teams, such as unambiguous specification for synthesis, interfaces and user-defined data types. Several design teams have embraced SystemVerilog as the language platform for future design.

The advantage of static analysis extends far beyond traditional error-detection. For example, static analysis data can be used to enable users to put together reusable modules, create portable code or to implement company-wide coding policies. VeriEZ's static analysis solution provides a way to enjoy all the benefits of static analysis by making available predefined rules (and sets of rules, called "rulesets") that can be invoked at the click of a button.

WHAT CAN WE DO FOR YOU?

Old habits die hard. One of the biggest hurdles in adopting SystemVerilog is understanding the new features provided by SystemVerilog, and using these features in an ongoing design process.

If you are developing your design or verification environment in Verilog, you can check if there are any SystemVerilog constructs that can be used in lieu of some Verilog constructs. EZCheck's SystemVerilog Guidance ruleset includes several checkers that analyze user code and suggest appropriate SystemVerilog-specific changes. For example:

• Using new constructs always_comb, always_ff, always_latch, always_* whenever possible
• Adopting new timeunit construct for consistency
• Using enumerations in place of parameters and pragmas for Finite State Machine design
• program and clocking blocks in testbench development

You can do all this, and more, with EZCheck.

ACT NOW

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