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VeriEZ Solutions Inc. Tools for Verification Engineers |
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OpenVera/NTB to SystemVerilog Migration |
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WHY IT MATTERS OpenVera continues to remain a very popular language to implement verification environments. In some cases, it may make sense to migrate the existing OpenVera environment to SystemVerilog. The decision to migrate to SystemVerilog and the actual migration can be a long process. Or, the verification team may put SystemVerilog on a watchlist, postponing the decision to translate to SystemVerilog. Whatever the reason, it may require writing SystemVerilog-compatible OpenVera. This strategy involves using constructs available in both languages, as well as using a restricted subset of OpenVera to conform to SystemVerilog restrictions and semantics. It is an immense help to have the help of tools to guide the engineer through this process. The advantage of static analysis extends far beyond traditional error-detection. For example, static analysis data can be used to enable users to put together reusable modules, create portable code or to implement company-wide coding policies. VeriEZ's static analysis solution provides a way to enjoy all the benefits of static analysis by making available predefined rules (and sets of rules, called "rulesets") that can be invoked at the click of a button. WHAT CAN WE DO FOR YOU? For ongoing development, VeriEZ's EZCheck can be used as a SystemVerilog guidance tool, where the engineer is informed of OpenVera code that will not port easily to SystemVerilog. For legacy OpenVera code, EZCheck can be used to get a summary of the portability of input code. This summary can be used as a basis to estimate the time required for the actual translation and the final translation. EZTranslate can be used to create equivalent SystemVerilog from OpenVera sources. EZCheck and EZTranslate provide a comprehensive environment for OpenVera to SystemVerilog migration. ACT NOW! Product Details Request Evaluation Ask us a question More information on SystemVerilog
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