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June 2, 2008: VeriEZ strengthens EZVerify with OVM and SystemVerilog Portability Checks
May 7, 2007: VeriEZ announces SystemVerilog® Design and Verification Productivity Tool Suite July 10, 2006: VeriEZ’s Static Analysis Technology Put To Unique Use - Checkers for Verilog® and SVA users designed to accelerate language usage
May 23, 2005: VeriEZ Solutions Enables Mixed-language Verification - EZVerify Enhanced to Support OpenVera® - SystemVerilog® Co-Development May 3, 2004: VeriEZ Introduces Vera®-to-SystemVerilog® 3.1 Migration Tool Suite May 22, 2003: VeriEZ Solutions introduces industry’s first OpenVera® Productivity Tool Suite
In the News synopsys.com (June 5, 2007): Synopsys Launches VMM Catalyst Program With More Than 50 Member Companies
eedesign.com: (May 8, 2007): Static checker completes SystemVerilog support
eedesign.com (May 26, 2005): Verification tool adds SystemVerilog support eedesign.com (April 30, 2004): Translator ties Vera code to SystemVerilog 3.1 eedesign.com: Commentary in EDA Views section by president and CEO, Sashi Obilisetty EETimes ( May 28, 2003 ) : EDA startup offers linter for OpenVera testbench language
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