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EZVerify is
the industry's first Design and Verification Productivity ToolSuite.
It is a high-performance design and verification
productivity tool suite for OpenVera® and SystemVerilog-based
design and verification teams. To enable efficient
verification, EZVerify uses a three-pronged attack -
- identifies
coding errors early in the flow, giving
beginner and experienced users alike the opportunity to
fix such errors
-
allows development of reusable design and verification modules,
and
- provides a
comprehensive document of design and verification information by
analyzing the input modules (new, legacy or external
IP).
EZVerify consists of two components
–
- EZCheck - Static
Lint and Rule Checker
- EZReport -
Design and Verification Knowledge Extractor
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Benefits |
Features |
- Accelerates
Verification
- Allows
companies to implement a corporate-wide
coding policy
- Enables
smooth integration of geographically
dispersed product teams
- Performs
quantitative analysis of external
design and verification IP
- Provides
easy mechanism to understand and integrate
legacy design and verification modules
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- Full
language support for SystemVerilog and OpenVera
- Fits into
existing design and verification flows
- Provides
in-memory knowledge base that can be
accessed with intuitive API
- Highly
extensible - robust API provides foundation
for infinite user extensions
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High-performance
- Platforms -
Solaris and Linux
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