EZTranslate is the industry’s first comprehensive Tool Suite that enables translation of OpenVera modules to SystemVerilog.

Over the past decade, OpenVera® has become a popular language to implement verification plans. Several companies building cutting-edge electronic products have used Vera successfully in their verification flow. SystemVerilog 3.1a, the next generation of Verilog®, which includes verification-ready constructs is being viewed by users and vendors alike as a viable verification language. SystemVerilog 3.1a-based verification teams can be vendor-independent, and realize cost-savings by utilizing the simulator’s testbench capabilities.

EZTranslate provides a clear path to companies looking for a Vera to SystemVerilog migration path. It can be used to enforce a SystemVerilog-compatible Vera development policy for ongoing projects and to migrate existing Vera code to SystemVerilog.

Benefits:

• Enforce SystemVerilog-compatible OpenVera development policy
• Reuse existing Vera modules in SystemVerilog-based verification environment
   

Features:

• Full language support for OpenVera
• User-extensible, portability ruleset can be updated as standard evolves
• Platforms: Solaris and Linux