EZReport - Verification Knowledge Extractor

              
Overview     Use Model     Doxygen Interface    GUI Shots

Overview

EZReport creates a comprehensive document that summarizes the design and verification aspects of a given SystemVerilog or OpenVera module. It takes as input a list of Hardware Design Verification Language (HVL) modules, and creates an HTML document with the following information:

* Class hierarchy
* Module hierarchy
* Top-level program
* Synchronization mechanisms
* Global variables and subroutines
* Interfaces and connections
 

Use Model

EZReport is useful to understand external verification IP and legacy IP. Verification engineers can make reuse decisions by using the comprehensive document created by EZReport. Users may also customize the document created to include additional proprietary information such as links to specific files and illustrations.

DOXYGEN INTERFACE

EZReport comes standard with a built-in interface to Doxygen, a popular documentation extraction tool for Java and C++. EZReport's interface includes the ability to correctly prepare OpenVera and SystemVerilog files as input to Doxygen.

BENEFITS

Instant design and verification reuse platform

Shareable, web-ready documents

Consolidate and enable superior IP creation process

Automatic extraction of design and verification knowledge

Intuitive class hierarchy snapshot

Valuable summary of synchronization
mechanisms

FEATURES

Full language support for SystemVerilog® and OpenVera®

Elegant integration with Doxygen

HTML output with customizable style sheets

Fits into existing flow

High-performance - runs very fast

Platforms - Solaris and Linux