If you would like to be considered for job openings in the company, please send your resume to jobs@veriez.com. General requirements for key positions:

Software Engineering: BS in Computer Science/EE is required. Depending on the position, relevant experience may be required. Experience in EDA software development, C and object-oriented (C++/Java) based programming is required for all positions. Knowledge of Verilog, VHDL and ASIC and IC design and verification process is a plus.

Sales/Marketing/Applications: BS required. MBA is a plus for sales and marketing professionals. Application Engineering applicants should have relevant field experience in front-end design and verification. All applicants should have relevant EDA experience.

Job Title: Member of Technical Staff

Duties: Design and develop software products and solutions for design verification of ASICs and FPGAs; enhance VeriEZ's functional verification static analysis technology, develop verification knowledge extractor for OpenVera and SystemVerilog, develop the SystemVerilog front-end for functional verification static analysis, develop tools and solutions to help customers migrating from OpenVera to SystemVerilog and from Verilog to SystemVerilog, identify and resolve customer support issues.

Requirement: M.S. in Compter Science or related. In depth knowledge of C++, OOP concepts, hardware-oriented data structure design, API design, CAD algorithms; expertise in scripting using Perl/Shell required. Must have knowledge of HDL, HVL, HDL-based methodologies, assertions-based verification.