WHY IT MATTERS

Verilog is a popular language used by DV engineers to implement their verification environment. SystemVerilog offers several valuable features for such verification teams, such as constrained-random stimulus generation, functional coverage, object-oriented programming support and built-in concurrency. Several DV teams have embraced SystemVerilog as the language platform for verification. SystemVerilog's leadership as the verification engineer's first choice is further cemented by overwhelming support by EDA vendors and a rich array of supporting tools.

The advantage of static analysis extends far beyond traditional error-detection. For example, static analysis data can be used to enable users to put together reusable modules, create portable code or to implement company-wide coding policies. VeriEZ's static analysis solution provides a way to enjoy all the benefits of static analysis by making available predefined rules (and sets of rules, called "rulesets") that can be invoked at the click of a button.

WHAT CAN WE DO FOR YOU?

Old habits die hard. One of the biggest hurdles in adopting SystemVerilog is understanding the new features provided by SystemVerilog, and using these features in ongoing testbench development.

If you are developing your verification environment in Verilog, you can check if there are any SystemVerilog constructs that can be used in lieu of some Verilog constructs. EZCheck's SystemVerilog Guidance ruleset includes several checkers that analyze user code and suggest appropriate Systemverilog-specific changes. For example:

• Replacing top-level testbench module with program and/or clocking blocks
• Replacing exit paths and simulation control constructs with corresponding immediate assertions

You can do all this, and more, with EZCheck.

ACT NOW!

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