|
VeriEZ Solutions Inc. Tools for Verification Engineers |
|
|
|
|
|
DV Engineers using SystemVerilog Testbench |
|
|
WHY IT MATTERS By some accounts, a significant subset of DV engineers rely on indigenously developed tools, scripts and libraries to execute their verification goals. SystemVerilog offers several valuable features for such verification teams, such as constrained-random stimulus generation, functional coverage, object-oriented programming support and built-in concurrency. Several DV teams have embraced SystemVerilog as the language platform for verification. SystemVerilog's leadership as the verification engineer's first choice is further cemented by overwhelming support by EDA vendors and a rich array of supporting tools. Like in any programming language, it is easy to make mistakes when writing code. No, we are not talking about syntax and semantic errors. We are talking about issues in code that "appear" to be erroneous. For e.g., lets take the following scenarios:
In most cases, the situations outlined above could be programming errors. Simulation and testbench tools will not trap these cases. We think it makes sense to warn the engineer about such conditions encountered in the code. Our solution analyzes code statically to detect errors in user code. The advantage of static analysis extends far beyond traditional error-detection. For example, static analysis data can be used to enable users to put together reusable modules, create portable code or to implement company-wide coding policies. VeriEZ's static analysis solution provides a way to enjoy all the benefits of static analysis by making available predefined rules (and sets of rules, called "rulesets") that can be invoked at the click of a button. WHAT CAN WE DO FOR YOU? VeriEZ's EZCheck can be used to exploit the power of static analysis for efficient design and verification. It provides 325+ predefined rules and several rulesets that target error-free code development, best practices for functional coverage model design, object-oriented programming methodology, assertion-based verification and SystemVerilog Migration. Once you have developed your verification environment in SystemVerilog, you can:
You may also want to:
You can do all this, and more, with EZCheck. ACT NOW! Product Details Request Evaluation Ask us a question More information on SystemVerilog
|
|
|