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VeriEZ Solutions Inc. Tools for Verification Engineers |
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DV Engineers using Open Verification Methodology / Verification Methodology Manual |
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WHY IT MATTERS Advanced verification methodologies have taken the verification industry by storm. SystemVerilog's many valuable features have been skillfully used to create methodologies such as OVM (Open Verification Methodology) and VMM (Verification Methodology Manual). By adopting these methodologies in their flow, verification engineers can put together reusable and scalable verification environments more efficiently. While these methodologies enhance productivity significantly, there is an associated learning curve. Further, like with any language-based methodology, there is a potential for errors to creep in. For e.g., lets take the following scenarios:
In most cases, simulation and testbench tools will not trap these cases. We think it makes sense to warn the engineer about such conditions encountered in the code. Our solution analyzes code statically to detect errors in user code. The advantage of static analysis extends far beyond traditional error-detection. For example, static analysis data can be used to enable users to put together reusable modules, create portable code or to implement company-wide coding policies. VeriEZ's static analysis solution provides a way to enjoy all the benefits of static analysis by making available predefined rules (and sets of rules, called "rulesets") that can be invoked at the click of a button. WHAT CAN WE DO FOR YOU? VeriEZ's EZCheck can be used in VMM and OVM based environments to check for erroneous code, such as non-compliant objects, missing methods and messaging non-compliance. For more details, follow these links: OVM, VMM ACT NOW! Product Details Request Evaluation Ask us a question More information on SystemVerilog
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