DV Engineers using SystemVerilog Testbench

WHY IT MATTERS

With EDA simulation platforms not currently supporting the entire language or due to differences in the interpretation of the 1800 standard by EDA vendors, it is possible to write SystemVerilog code that compiles on one simulator, but fails to compile on another. IP development demands portable SystemVerilog modules.

For e.g., consider the following code:

//SystemVerilog code that will compile without problems – but is it portable?

timeunit 100 ns;
timeprecision 10 ps;

program prg;

function bit test;
bit temp;
temp = 1;
test = temp;
if (temp == 0)
return;
task1();
endfunction

task task1();
//..
endtask

function int calculate(ref int val);
val = val + 1;
calculate = val;
endfunction

class cc;
reg a;
extern task t1(int i);
extern function int t2(int i = 0);
endclass;

initial
begin
$display("This is a compliance example");
end

//out of body declaration here
task cc::t1(int i);
endtask

function int cc::t2(int i);
endfunction
endprogram

The above code will compile on one industry standard simulator, but fail on another.

Can you find 5 errors in the above "SystemVerilog" code? Send us your answer, and we will send you a free movie ticket.

The advantage of static analysis extends far beyond traditional error-detection. For example, static analysis data can be used to enable users to put together reusable modules, create portable code or to implement company-wide coding policies. VeriEZ's static analysis solution provides a way to enjoy all the benefits of static analysis by making available predefined rules (and sets of rules, called "rulesets") that can be invoked at the click of a button.

WHAT CAN WE DO FOR YOU?

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