WHY IT MATTERS

Early error detection in HDL-based designs can save you time and money! An unintentional latch here, and an unassigned net there can be all that is needed to cause a chip to fail. It is no surprise that RTL Lint has become all pervasive in the design world, and is consistently the first tool used in the synthesis flow.

Not all lint tools are created equal. In recent times, the word "lint" has evolved to include everything from static analysis to coding policy compliance. For example, most design teams have naming and documentation policies to facilitate good coding practices, better maintainability and extensive reuse.

A good static analysis tool should be cheap, fast, and effective. By invoking the static analysis tool, the user should be able to detect errors and coding that can be detected by static analysis, and display results to the user in an easy-to-navigate fashion.

By some accounts, a significant subset of DV engineers rely on indigenously developed tools, scripts and libraries to execute their verification goals.

WHAT CAN WE DO FOR YOU?

VeriEZ's EZCheck can be used to exploit the power of static analysis for efficient design and verification. It provides 325+ predefined rules and several rulesets that target error-free code development, best practices for functional coverage model design, object-oriented programming methodology, assertion-based verification and SystemVerilog Migration.

ACT NOW!

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