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PRESS RELEASE
VeriEZ strengthens EZVerify with OVM and
SystemVerilog Portability Checks
OVM and Portability modules further enhance productivity of
SystemVerilog-based teams
Santa Clara, CA – June 2, 2008 -- VeriEZ Solutions, Inc., the
Verification Tools Company, today announced the availability of new
modules for EZVerify, the industry’s premier SystemVerilog
Productivity tool suite for Design and Verification Engineers. Newly
available modules for Open Verification Methodology (OVM) and
SystemVerilog Portability fit seamlessly into existing design and
verification environments.
“SystemVerilog adoption has been phenomenal,” said Sashi Obilisetty,
VeriEZ’s president and CEO. “It is now time to supply engineers with
tools to fully exploit SystemVerilog’s many features. Our OVM and
SystemVerilog Portability modules can be put to immediate use by
design and verification teams.”
EZVerify utilizes static analysis techniques to provide an
environment for creating reusable and error-free modules in
SystemVerilog. It consists of two components: EZCheck (configurable
static analyzer) and EZReport (verification knowledge extractor).
EZCheck parses SystemVerilog files, and applies selected “rulesets”
(rule collections) to user-supplied input. Prepackaged rulesets are
included for Design Analysis (for RTL Synthesis), Functional
Coverage Model and Verification Analysis (for verification models),
Assertions Analysis (for ABV), Model Portability and Verification
Methodology Manual (VMM) productivity.
EZReport is designed to provide an instant reuse platform for
product teams. EZReport creates comprehensive knowledge documents
that enable engineers to understand existing components and make
reuse decisions. EZReport includes required interfaces to generate
documentation in the Doxygen format.
OVM Module
The OVM module checks for compliance of user input with OVM-specific
guidelines. OVM is an IEEE 1800-compliant advanced verification
methodology that enables creation of reusable environments. OVM’s
scalable architecture, open licensing, and broad vendor support have
established it as one of the industry’s premier verification
methodologies.
The OVM module’s 25+ checks focus on four main areas:
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Object
Design
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OVM
Best Practices
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Connectivity
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Verification Environment
SystemVerilog Portability Module
The SystemVerilog Portability module addresses a critical issue in
today’s SystemVerilog environments. In part due to its status as an
active and emerging standard, the SystemVerilog language is not
supported consistently across synthesis and simulation platforms.
This makes development of portable SystemVerilog modules impossible.
The SystemVerilog Portability module’s 30+ checks keep the user
informed about current requirements for writing portable and
1800-compliant SystemVerilog modules. Checks in this module include
(but are not limited to):
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1800 compliance for
functions and function return values
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Class prototype and
method signatures
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Detection of
non-standard SystemVerilog 3.1a constructs
Pricing and Availability
EZVerify for SystemVerilog, including the SystemVerilog Portability
module, is available now. New module for OVM will debut at DAC 2008,
and be available immediately thereafter. Annual licensing fees
starts at $20,000 USD.
VeriEZ product demonstrations can be viewed in VeriEZ’s booth
(#1936) at DAC (June 9-12, 2008, Anaheim, California).
About VeriEZ
VeriEZ Solutions, Inc. is a privately held EDA company that develops
and markets solutions that enable efficient chip verification. It is
the developer of EZVerify and EZTranslate Tool Suites. EZVerify is
the industry’s first Design and Verification Productivity Tool Suite
for SystemVerilog® and OpenVera™. It includes a configurable static
analyzer (EZCheck) and a verification knowledge extractor (EZReport).
EZTranslate is an OpenVera-to-SystemVerilog Migration Tool Suite.
VeriEZ’s tools detect errors and enable reuse. More information is
available on the company website,
www.veriez.com.
Contact:
Sashi Obilisetty
President & CEO
Ph: (408)-988-1604 ext. 1 / em: sashi_at_veriez.com
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