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See us at DAC, June 8-12, 2008
Request Meeting
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Demos @ DAC
- SystemVerilog
Design and Verification
Productivity using EZVerify
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OVM
Productivity using EZVerify
- rule-checking and Doxygen-based
documentation
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VMM
Productivity using EZVerify
- rule-checking and Doxygen-based
documentation
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EZTranslate: A
production-proven OpenVera to
SystemVerilog Migration platform
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VeriEZ Solutions
for:
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VeriEZ Solutions by category:
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VeriEZ develops and markets software
products and solutions used to enable efficient
functional design and verification of electronic systems and
integrated circuits (IC).
It is
well-known that up to 70% of a design team's resources
are spent on verification. Verification of such complex
systems poses a tremendous challenge to both the
designer and the vendor who provides solutions to verify
such systems. VeriEZ was founded to address the
verification challenge. We are building products and
solutions that will cut down the time spent on
verification. Companies will see immediate benefits from
using VeriEZ products and solutions.
VeriEZ's EZVerify is
the industry's first Design and Verification Productivity Tool Suite.
EZVerify is a high-performance verification
productivity tool suite for SystemVerilog and OpenVera® based
design and verification teams. To enable efficient
verification, EZVerify uses a three-pronged attack -
- identifies errors early in the flow, giving
beginner and experienced users alike the opportunity to
fix such errors
- allows users to build
reusable verification modules,
and
- provides a
comprehensive document of design and verification information by
analyzing the input modules (new, legacy or external
verification IP).
EZVerify consists of two components
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- EZCheck - Static
Lint Checker for design and verification modules
- EZReport -
Design and Verification Knowledge Extractor
EZTranslate is the industry’s first
comprehensive Tool Suite that enables translation of
OpenVera modules to SystemVerilog. Over the past decade,
OpenVera® has become a popular language to implement
verification plans. By using EZTranslate, users can
immediately leverage their OpenVera modules in a
SystemVerilog environment.
VeriEZ is located in Santa Clara,
California. It is privately funded. If you would like to
get more information about the company or our products,
please click
here.
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